This invention relates to semiconductor device packages or housings and more specifically relates to a novel clip-type lead frame for a semiconductor device.
Semiconductor devices, particularly power MOSFETs are frequently mounted on a conductive lead frame which is overmolded with an insulation housing. Leads extend from the lead frame through the housing for external connection to electrical circuits.
Advances in semiconductor processing technology, however, have made the parasitics associated with conventional packages more of a performance limiting factor. This is particularly true in the case of power switching devices where, as in the case of power MOSFETs, the on-resistance of these devices continues to push the lower limits. Thus, the parasitic resistance introduced by the lead frame in conventional packages becomes much more significant for very high current devices such as power MOSFETs.
It would be very desirable to provide a very thin (low profile) surface mount package which lends itself to low cost manufacture, and which reduces the area (or foot print) of the lead frame and which has excellent thermal and electrical properties and which reduces lead frame scrap.
In accordance with the invention, a novel lead frame is provided for a small volume package, for example, and SO8 type package, that has a central strip which is upwardly displaced out of the plane of the lead frame for receiving the source electrode surface, or other power electrode of a semiconductor die. The die is then nested within the lead frame with its top surface against the bottom of the displaced central source strap. The bottom of the die, and thus the drain electrode of a power MOSFET die protrudes from the bottom surface of a plastic housing which encapsulates the die and lead frame.
The resulting device is a surface mountable device which can be made with inexpensive and reliable techniques and has excellent thermal and electrical properties. The device can be easily bonded to support surfaces and is an ultra thin package. The footprint area occupied by a chip scale package is typically less than or equal to 1.5 times that of the die area contained within the package (taken from IPC CSP definition). Alternatively, in certain cases the package size is chip scale, that is, the package area is approximately equal to the die area, and precious metal use and waste material is reduced. Finally, the novel device has very good thermal and electrical properties with reduced parasites.